document level/sense encoding info for IPIC
interrupt controllers
Signed-off-by: Stuart Yoder <[EMAIL PROTECTED]>
---
Documentation/powerpc/booting-without-of.txt | 19 ++++++++++++++++++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt
b/Documentation/powerpc/booting-without-of.txt
index c169299..e7a465c 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -50,13 +50,14 @@ Table of Contents
g) Freescale SOC SEC Security Engines
h) Board Control and Status (BCSR)
i) Freescale QUICC Engine module (QE)
- g) Flash chip nodes
+ j) Flash chip nodes
VII - Specifying interrupt information for devices
1) interrupts property
2) interrupt-parent property
3) OpenPIC Interrupt Controllers
4) ISA Interrupt Controllers
+ 5) IPIC Interrupt Controllers
Appendix A - Sample SOC node for MPC8540
@@ -1878,6 +1879,22 @@ encodings listed below:
2 = high to low edge sensitive type enabled
3 = low to high edge sensitive type enabled
+5) Freescale IPIC Interrupt Controllers
+---------------------------------------
+
+IPIC interrupt controllers are specific to Freescale 83xx
+SOCs. Two cells are required to encode interrupt information.
+The first cell defines the interrupt number. The second cell
+defines the sense and level information.
+
+Sense and level information follows the Linux convention
+(specified in include/linux/interrupt.h) and should be encoded
+as follows:
+
+ 2 = high to low edge sense type enabled
+ 8 = active low level sense type enabled
+
+Note: other level/sense types (0,1,4, etc) are not supported.
Appendix A - Sample SOC node for MPC8540
========================================
--
1.5.0.3
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