> From: Mason
> Sent: 06 March 2017 15:46
...
> >> The issue was that, on this platform, the PCI configuration space
> >> and memory space are multiplexed; in other words they reside at
> >> the same physical address, with a bit in MMIO to choose one or
> >> the other.
> >
> > Time to shoot another hardware engineer.
>
> He's in CC :-)
>
> > Hopefully it isn't an SMP system - but I wouldn't put it past them.
>
> This is a dual- and quad- Cortex A9 MP platform :-(
So to do a config space access you have to use a pair of IPIs
to stop the other cpus doing any PCIe data accesses while the
MMIO bit makes the accesses all point to config space.
(After taking a lock to get access to the MMIO register.)
Or has someone a better idea?
David
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