Hi, Rob Herring <r...@kernel.org> writes: >> Synopsys HW setup (HAPS DX and phy board) requires a preset to this >> register to improve interoperablitity. For example, the value for >> GFLADJ_REFCLK_LPM_SEL should be set to 0 with ref_clk period of 50. > > This sounds like it should be handled in the driver. Is it a simple, > constant correlation of ref_clk period to this value?
you mean that this could be calculated based off of clk_get_rate() ? -- balbi
signature.asc
Description: PGP signature
