Hi John, > John Youn <johny...@synopsys.com> hat am 1. September 2016 um 23:07 > geschrieben: > > > This series accounts for the delay from the IDDIG debounce filter when > switching modes. This delay is a function of the PHY clock speed and > can range from 5-50 ms. This delay must be taken into account on core > reset and force modes. A full explanation is provided in the patch > commit log and code comments. > > This revision of the series increases the IDDIG delay to 100 ms. Some > rockchip platforms seem to timeout even with 50 ms so I have doubled > this. > > Appreciate any testing on RK3188 and RPi platforms.
i tested the whole series successful with a Raspberry Pi B in dr_mode "host" and "otg" Tested-by: Stefan Wahren <stefan.wah...@i2se.com> -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
