> Le Mon, 29 Jun 2015 16:40:52 +0800, > Peter Chen <peter.c...@freescale.com> a écrit : > > > I am not sure if you have noticed the patch[1], it is the solution for > > this issue, in the RTL, the default reserved time for one packet is > > 1023 bytes for siTD, so after 4 * 64 packets has transfered, the > > reserved time is not enough for 1023 bytes packet. > > > > This issue should exist at all ARC/Chipidea cores. > In that case can't we enable the patch for all cores instead of using platform > data flags ? > Hi Matthieu
This bit may also affects QH, we only make sure Freescale's part QH design does not be affected by this tt ctrl bits, but doesn't know other vender's. Peter
