From: Peter Chen
> The phy needs some delay to output the stable status from low
> power mode. And for OTGSC, the status inputs are debounced
> using a 1 ms time constant, so, delay 2ms for controller to get
> the stable status(like vbus and id) when the phy leaves low power.
>
> Signed-off-by: Peter Chen <peter.c...@freescale.com>
> ---
> drivers/usb/chipidea/core.c | 24 ++++++++++++++++--------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> index 409aba3..ac7aa7e 100644
> --- a/drivers/usb/chipidea/core.c
> +++ b/drivers/usb/chipidea/core.c
> @@ -189,6 +189,17 @@ u8 hw_port_test_get(struct ci_hdrc *ci)
> return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
> }
>
> +static void hw_wait_phy_stable(void)
> +{
> + /*
> + * The phy needs some delay to output the stable status from low
> + * power mode. And for OTGSC, the status inputs are debounced
> + * using a 1 ms time constant, so, delay 2ms for controller to get
> + * the stable status, like vbus and id when the phy leaves low power.
> + */
> + usleep_range(2000, 2500);
> +}
> +
> /* The PHY enters/leaves low power mode */
> static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
> {
> @@ -307,7 +318,9 @@ static int ci_usb_phy_init(struct ci_hdrc *ci)
> case USBPHY_INTERFACE_MODE_UTMIW:
> case USBPHY_INTERFACE_MODE_HSIC:
> ret = usb_phy_init(ci->transceiver);
> - if (ret)
> + if (!ret)
> + hw_wait_phy_stable();
> + else
> return ret;
Why invert the condition.
> hw_phymode_configure(ci);
> break;
> @@ -320,6 +333,8 @@ static int ci_usb_phy_init(struct ci_hdrc *ci)
> break;
> default:
> ret = usb_phy_init(ci->transceiver);
> + if (!ret)
> + hw_wait_phy_stable();
> }
>
> return ret;
> @@ -620,13 +635,6 @@ static int ci_hdrc_probe(struct platform_device *pdev)
> if (ret) {
> dev_err(dev, "unable to init phy: %d\n", ret);
> return ret;
> - } else {
You don't need else after return.
David
> - /*
> - * The delay to sync PHY's status, the maximum delay is
> - * 2ms since the otgsc uses 1ms timer to debounce the
> - * PHY's input
> - */
> - usleep_range(2000, 2500);
> }
>
> ci->hw_bank.phys = res->start;
> --
> 1.7.9.5
>
> --
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