According to user manual, pcs_tx_deemph_3p5db field in PHYPARAM1
register is 6bits wide, so mask value should be 0x3f instead
of 0x1f. Additionally, this patch renames the macro to correctly
reflect the field name which we see in SoC documentation.
Signed-off-by: Anton Tikhomirov <av.tikhomi...@samsung.com>
---
drivers/phy/phy-exynos5-usbdrd.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-
usbdrd.c
index 392101c..216bbf8 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -99,8 +99,8 @@
#define EXYNOS5_DRD_PHYPARAM1 0x20
-#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
-#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+#define PHYPARAM1_PCS_TXDEEMPH_3P5DB_MASK (0x3f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH_3P5DB (0x1c)
#define EXYNOS5_DRD_PHYTERM 0x24
@@ -309,8 +309,8 @@ static void exynos5_usbdrd_pipe3_init(struct
exynos5_usbdrd_phy *phy_drd)
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
/* Set Tx De-Emphasis level */
- reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
- reg |= PHYPARAM1_PCS_TXDEEMPH;
+ reg &= ~PHYPARAM1_PCS_TXDEEMPH_3P5DB_MASK;
+ reg |= PHYPARAM1_PCS_TXDEEMPH_3P5DB;
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
@@ -330,8 +330,8 @@ static void exynos5_usbdrd_utmi_init(struct
exynos5_usbdrd_phy *phy_drd)
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
/* Set Tx De-Emphasis level */
- reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
- reg |= PHYPARAM1_PCS_TXDEEMPH;
+ reg &= ~PHYPARAM1_PCS_TXDEEMPH_3P5DB_MASK;
+ reg |= PHYPARAM1_PCS_TXDEEMPH_3P5DB;
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
/* UTMI Power Control */
--
1.7.9.5
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