Dear Peter Chen,

> With the auto setting, the PHY's clock and power can be
> recovered correctly from low power mode, it is ganranteed by IC logic.
> 
> Besides, we enable the IC fixes for this PHY at mx6 platform.
> 
> Signed-off-by: Peter Chen <peter.c...@freescale.com>
> ---
>  drivers/usb/phy/phy-mxs-usb.c |   30 ++++++++++++++++++++++++++----
>  1 files changed, 26 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
> index f80e2e6..868c445 100644
> --- a/drivers/usb/phy/phy-mxs-usb.c
> +++ b/drivers/usb/phy/phy-mxs-usb.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
>   * Copyright (C) 2012 Marek Vasut <ma...@denx.de>
>   * on behalf of DENX Software Engineering GmbH
>   *
> @@ -29,8 +29,17 @@
>  #define HW_USBPHY_CTRL_SET                   0x34
>  #define HW_USBPHY_CTRL_CLR                   0x38
> 
> +#define HW_USBPHY_IP                         0x90
> +#define HW_USBPHY_IP_SET                     0x94
> +#define HW_USBPHY_IP_CLR                     0x98
> +
>  #define BM_USBPHY_CTRL_SFTRST                        BIT(31)
>  #define BM_USBPHY_CTRL_CLKGATE                       BIT(30)
> +#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS     BIT(26)
> +#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE  BIT(25)
> +#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD     BIT(20)
> +#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE     BIT(19)
> +#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL              BIT(18)
>  #define BM_USBPHY_CTRL_ENUTMILEVEL3          BIT(15)
>  #define BM_USBPHY_CTRL_ENUTMILEVEL2          BIT(14)
>  #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT    BIT(1)
> @@ -100,11 +109,24 @@ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
>       /* Power up the PHY */
>       writel(0, base + HW_USBPHY_PWD);
> 
> -     /* enable FS/LS device */
> -     writel(BM_USBPHY_CTRL_ENUTMILEVEL2 |
> -            BM_USBPHY_CTRL_ENUTMILEVEL3,
> +     /*
> +      * USB PHY Ctrl Setting
> +      * - Auto clock/power on
> +      * - Enable full/low speed support
> +      */
> +     writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
> +             BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
> +             BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
> +             BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
> +             BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
> +             BM_USBPHY_CTRL_ENUTMILEVEL2 |
> +             BM_USBPHY_CTRL_ENUTMILEVEL3,
>              base + HW_USBPHY_CTRL_SET);
> 
> +     /* Enable IC solution */
> +     if (is_mx6q_phy(mxs_phy) || is_mx6sl_phy(mxs_phy))
> +             writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);

So why not just add fsl,imx6-phy instead of adding three phy types ?

Best regards,
Marek Vasut
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