On Wed, 16 Jan 2013, Venu Byravarasu wrote:
> As Tegra PHY driver needs to access one of the Host registers,
> added few APIs.
>
> Signed-off-by: Venu Byravarasu <vbyravar...@nvidia.com>
> --- a/drivers/usb/host/ehci-tegra.c
> +++ b/drivers/usb/host/ehci-tegra.c
> @@ -605,6 +619,50 @@ static const struct dev_pm_ops tegra_ehci_pm_ops = {
>
> #endif
>
> +void tegra_ehci_set_wakeon_events(struct usb_phy *x, bool enable)
> +{
> + unsigned long val;
> + struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
> + void __iomem *base = hcd->regs;
> + u32 wake = USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
> +
> + val = readl(base + USB_PORTSC1);
> + if (enable)
> + val |= wake;
> + else
> + val &= ~wake;
> + writel(val, base + USB_PORTSC1);
> +}
Here and below, this sort of code is highly questionable. You
evidently don't realize that some of the bits in the PORTSC registers
are R/WC. This means writing a 1 to these bits will clear them.
Consequently it is almost always wrong to read a PORTSC register and
then write back the same (or a slightly modified) value.
Alan Stern
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