tree: https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git testing/next head: 2e3cfcbbb1403feeac5949f32dcd2724de3ff40c commit: a0a493835f9a2e4c690c41145def88223997db2b [19/42] usb: dwc2: optionally assert phy reset when waking up config: x86_64-randconfig-x000-201916 (attached as .config) compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 reproduce: git checkout a0a493835f9a2e4c690c41145def88223997db2b # save the attached .config to linux build tree make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <l...@intel.com>
All errors (new ones prefixed by >>):
drivers/usb/dwc2/core_intr.c: In function 'dwc2_handle_wakeup_detected_intr':
>> drivers/usb/dwc2/core_intr.c:448:25: error: 'struct dwc2_hsotg' has no
>> member named 'phy_reset_work'
schedule_work(&hsotg->phy_reset_work);
^~
vim +448 drivers/usb/dwc2/core_intr.c
388
389 /*
390 * This interrupt indicates that the DWC_otg controller has detected a
391 * resume or remote wakeup sequence. If the DWC_otg controller is in
392 * low power mode, the handler must brings the controller out of low
393 * power mode. The controller automatically begins resume signaling.
394 * The handler schedules a time to stop resume signaling.
395 */
396 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
397 {
398 int ret;
399
400 /* Clear interrupt */
401 dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
402
403 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected
Interrupt++\n");
404 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__,
hsotg->lx_state);
405
406 if (hsotg->lx_state == DWC2_L1) {
407 dwc2_wakeup_from_lpm_l1(hsotg);
408 return;
409 }
410
411 if (dwc2_is_device_mode(hsotg)) {
412 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
413 dwc2_readl(hsotg, DSTS));
414 if (hsotg->lx_state == DWC2_L2) {
415 u32 dctl = dwc2_readl(hsotg, DCTL);
416
417 /* Clear Remote Wakeup Signaling */
418 dctl &= ~DCTL_RMTWKUPSIG;
419 dwc2_writel(hsotg, dctl, DCTL);
420 ret = dwc2_exit_partial_power_down(hsotg, true);
421 if (ret && (ret != -ENOTSUPP))
422 dev_err(hsotg->dev, "exit power_down
failed\n");
423
424 call_gadget(hsotg, resume);
425 }
426 /* Change to L0 state */
427 hsotg->lx_state = DWC2_L0;
428 } else {
429 if (hsotg->params.power_down)
430 return;
431
432 if (hsotg->lx_state != DWC2_L1) {
433 u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
434
435 /* Restart the Phy Clock */
436 pcgcctl &= ~PCGCTL_STOPPCLK;
437 dwc2_writel(hsotg, pcgcctl, PCGCTL);
438
439 /*
440 * If we've got this quirk then the PHY is
stuck upon
441 * wakeup. Assert reset. This will propagate
out and
442 * eventually we'll re-enumerate the device.
Not great
443 * but the best we can do. We can't call
phy_reset()
444 * at interrupt time but there's no hurry, so
we'll
445 * schedule it for later.
446 */
447 if (hsotg->reset_phy_on_wake)
> 448 schedule_work(&hsotg->phy_reset_work);
449
450 mod_timer(&hsotg->wkp_timer,
451 jiffies + msecs_to_jiffies(71));
452 } else {
453 /* Change to L0 state */
454 hsotg->lx_state = DWC2_L0;
455 }
456 }
457 }
458
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