Fine to me. Thanks!
Acked-by: Wei Li <liwei...@huawei.com>
-----邮件原件-----
发件人: Manivannan Sadhasivam [mailto:manivannan.sadhasi...@linaro.org]
发送时间: 2019年1月5日 15:29
收件人: vinholika...@gmail.com; j...@linux.vnet.ibm.com;
martin.peter...@oracle.com; liwei (CM); robh...@kernel.org
抄送: linux-scsi@vger.kernel.org; linux-ker...@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
john.stu...@linaro.org; amit.kuche...@linaro.org; guodong...@linaro.org;
Manivannan Sadhasivam
主题: [PATCH v2 2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support
Add UFS controller support for HiSilicon HI3670 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasi...@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 6ccdf5040ffd..285219dd657f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -654,6 +654,24 @@
clock-names = "apb_pclk";
};
+ /* UFS */
+ ufs: ufs@ff3c0000 {
+ compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3c0000 0x0 0x1000>,
+ <0x0 0xff3e0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ resets = <&crg_rst 0x84 12>;
+ reset-names = "rst";
+ };
+
/* SD */
dwmmc1: dwmmc1@ff37f000 {
compatible = "hisilicon,hi3670-dw-mshc";
--
2.17.1
