Thank you for the reply.
> On Wed, Mar 28, 2018 at 11:25:34AM +0000, Janek Kotas wrote:
>> This patch adds a device tree platform
>> driver description for Cadence UFS Controller.
>
> You have exactly the same subject for both patches. Don't do that. For
> bindings, the preferred subject prefix is “dt-bindings: ufs: “.
OK, I will change that in the next version of the path.
Thanks for letting me know.
>>
>> Signed-off-by: Jan Kotas <j...@cadence.com>
>> ---
>> .../devicetree/bindings/ufs/cdns-ufs-pltfrm.txt | 31
>> ++++++++++++++++++++
>> 1 files changed, 31 insertions(+), 0 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/ufs/cdns-ufs-pltfrm.txt
>>
>> diff --git a/Documentation/devicetree/bindings/ufs/cdns-ufs-pltfrm.txt
>> b/Documentation/devicetree/bindings/ufs/cdns-ufs-pltfrm.txt
>> new file mode 100644
>> index 0000000..d10229d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/ufs/cdns-ufs-pltfrm.txt
>
> rename to cdns,ufshc.txt
OK, I’ll change that.
>> @@ -0,0 +1,31 @@
>> +* Cadence Universal Flash Storage (UFS) Controller
>> +
>> +UFS nodes are defined to describe on-chip UFS host controllers.
>> +Each UFS controller instance should have its own node.
>> +
>> +Required properties:
>> +- compatible : compatible list, contains the following controller:
>> + "cdns,ufshc"
>> + complemented with the JEDEC version:
>> + "jedec,ufs-2.0"
>> +
>> +- reg : registers mapping
>> +- interrupts : interrupts mapping
>
> How many?
A single register and interrupt.
The description was based on the ufshcd-pltfrm.txt.
I’ll change it to be more descriptive.
>> +- clocks : List of phandle and clock specifier pairs.
>> +- clock-names : List of clock input name strings sorted in the same
>> + order as the clocks property. "core_clk" is mandatory.
>
> “_clk" is redundant.
Changed, thanks.
> Really only one clock for the block? No clock from the PHY? No bus
> clock?
I wasn’t sure how to handle that. The UFS controller block only requires
a core clock from a system. Symbol clocks come a PHY,
which is another, independent block.
Should I simply use a phys phandle, for a UFS PHY node?
>> +- freq-table-hz : Array of <min max> operating frequencies stored in
>> the same
>> + order as the clocks property. If this property is not
>> + defined or a value in the array is "0" then it is assumed
>> + that the frequency is set by the parent clock or a
>> + fixed rate clock source.
>
> The 'assigned-clocks' property and friends should be able to handle
> this.
The shared UFS platform code uses freq-table-hz,
I would like it to be consistent with the rest of the UFS drivers.
>> +
>> +Example:
>> + ufs@fd030000 {
>> + compatible = "cdns,ufshc", "jedec,ufs-2.0";
>> + reg = <0xfd030000 0x10000>;
>> + interrupts = <0 1 0>;
>> + freq-table-hz = <0 0>;
>> + clocks = <&ufs_core_clk 0>;
>> + clock-names = "core_clk";
>> + };
>> --
>> 1.7.1
