The correct LLC DLL phase depends on the board layout, so this
should be part of the platform_data.
Verified-by: Martin Bugge <marbu...@cisco.com>
Signed-off-by: Hans Verkuil <hans.verk...@cisco.com>
---
drivers/media/i2c/adv7842.c | 6 +-----
include/media/adv7842.h | 6 ++++++
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c
index 82c57d7..2eb4058 100644
--- a/drivers/media/i2c/adv7842.c
+++ b/drivers/media/i2c/adv7842.c
@@ -1591,9 +1591,6 @@ static void select_input(struct v4l2_subdev *sd,
afe_write(sd, 0x00, 0x00); /* power up ADC */
afe_write(sd, 0xc8, 0x00); /* phase control */
- io_write(sd, 0x19, 0x83); /* LLC DLL phase */
- io_write(sd, 0x33, 0x40); /* LLC DLL enable */
-
io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
/* script says register 0xde, which don't exist in manual */
@@ -2603,8 +2600,7 @@ static int adv7842_core_init(struct v4l2_subdev *sd)
io_write_and_or(sd, 0x20, 0xcf, 0x00);
/* LLC */
- /* Set phase to 16. TODO: get this from platform_data */
- io_write(sd, 0x19, 0x90);
+ io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
io_write(sd, 0x33, 0x40);
/* interrupts */
diff --git a/include/media/adv7842.h b/include/media/adv7842.h
index 8b336ab..c67051a 100644
--- a/include/media/adv7842.h
+++ b/include/media/adv7842.h
@@ -192,6 +192,12 @@ struct adv7842_platform_data {
unsigned sync:2;
} drive_strength;
+ /*
+ * IO register 0x19: Adjustment to the LLC DLL phase in
+ * increments of 1/32 of a clock period.
+ */
+ unsigned llc_dll_phase:5;
+
/* External RAM for 3-D comb or frame synchronizer */
unsigned sd_ram_size; /* ram size in MB */
unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
--
1.8.4.rc3
--
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