On Sun, May 12, 2019 at 02:00:04PM +0800, Louis Kuo wrote:
> This patch adds the DT binding documentation for the sensor interface
> module in Mediatek SoCs.
>
> Signed-off-by: Louis Kuo <louis....@mediatek.com>
> ---
> .../bindings/media/mediatek-seninf.txt | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/media/mediatek-seninf.txt
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek-seninf.txt
> b/Documentation/devicetree/bindings/media/mediatek-seninf.txt
> new file mode 100644
> index 000000000000..5c84a777acbd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek-seninf.txt
> @@ -0,0 +1,52 @@
> +* Mediatek seninf MIPI-CSI2 host driver
Bindings are for h/w blocks, not drivers...
How does this relate to the other series for Mediatek MIPI CSI2?
> +
> +Seninf MIPI-CSI2 host driver is a HW camera interface controller. It support
> a widely adopted,
> +simple, high-speed protocol primarily intended for point-to-point image and
> video
> +transmission between cameras and host devices.
> +
> +Required properties:
> + - compatible: "mediatek,mt8183-seninf"
> + - reg: Must contain an entry for each entry in reg-names.
> + - reg-names: Must include the following entries:
> + "base_reg": seninf registers base
> + "rx_reg": Rx analog registers base
'_reg' part is redundant.
> + - interrupts: interrupt number to the cpu.
> + - clocks : clock name from clock manager
> + - clock-names: must be CLK_CAM_SENINF and CLK_TOP_MUX_SENINF.
> + It is the clocks of seninf
> + - port : port for camera sensor
port is not a property
> + - port reg : must be '0' for camera 0, '1' for camera 1
> + - endpoint : config mipi-csi2 port setting for each camera
endpoint is not a property
> + - data-lanes : the number of the data lane
> +
> +Example:
> + seninf: seninf@1a040000 {
> + compatible = "mediatek,mt8183_seninf";
> + reg = <0 0x1a040000 0 0x8000>,
> + <0 0x11C80000 0 0x6000>;
> + reg-names = "base_reg", "ana_reg";
> + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>;
> + clocks =
The indentation is all wrong.
> + <&camsys CLK_CAM_SENINF>, <&topckgen
> CLK_TOP_MUX_SENINF>;
> + clock-names =
> + "CLK_CAM_SENINF", "CLK_TOP_MUX_SENINF";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + mipi_in_cam0: endpoint@0 {
> + reg = <0>;
> + data-lanes = <1 3>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + mipi_in_cam1: endpoint@0 {
> + reg = <1>;
> + data-lanes = <1 3>;
> + };
> + };
> + };
> + }
> --
> 2.18.0
>
