[PATCH 2/4] v4l2-fwnode: The first default data lane is 0 on C-PHY

[Sakari Ailus]

C-PHY has no clock lanes. Therefore the first data lane is 0 by default.

Fixes: edc6d56c2e7e ("media: v4l: fwnode: Support parsing of CSI-2 C-PHY 
endpoints")
Signed-off-by: Sakari Ailus <sakari.ai...@linux.intel.com>
---
 drivers/media/v4l2-core/v4l2-fwnode.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c 
b/drivers/media/v4l2-core/v4l2-fwnode.c
index 93d0547779df..6b990c78c73a 100644
--- a/drivers/media/v4l2-core/v4l2-fwnode.c
+++ b/drivers/media/v4l2-core/v4l2-fwnode.c
@@ -229,6 +229,10 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct 
fwnode_handle *fwnode,
        if (bus_type == V4L2_MBUS_CSI2_DPHY ||
            bus_type == V4L2_MBUS_CSI2_CPHY || lanes_used ||
            have_clk_lane || (flags & ~V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)) {
+               /* Only D-PHY has a clock lane. */
+               unsigned int dfl_data_lane_index =
+                       bus_type == V4L2_MBUS_CSI2_DPHY;
+
                bus->flags = flags;
                if (bus_type == V4L2_MBUS_UNKNOWN)
                        vep->bus_type = V4L2_MBUS_CSI2_DPHY;
@@ -237,7 +241,7 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct 
fwnode_handle *fwnode,
                if (use_default_lane_mapping) {
                        bus->clock_lane = 0;
                        for (i = 0; i < num_data_lanes; i++)
-                               bus->data_lanes[i] = 1 + i;
+                               bus->data_lanes[i] = dfl_data_lane_index + i;
                } else {
                        bus->clock_lane = clock_lane;
                        for (i = 0; i < num_data_lanes; i++)
-- 
2.11.0