Hi Maxime,
On Wed, 10 Jan 2018 16:37:24 +0100
Maxime Ripard <[email protected]> wrote:
> Hi Hugues,
>
> On Mon, Jan 08, 2018 at 05:13:39PM +0000, Hugues FRUCHET wrote:
> > I'm using a ST board with OV5640 wired in parallel bus output in order
> > to interface to my STM32 DCMI parallel interface.
> > Perhaps could you describe your setup so I could help on understanding
> > the problem on your side. From my past experience with this sensor
> > module, you can first check hsync/vsync polarities, the datasheet is
> > buggy on VSYNC polarity as documented in patch 4/5.
>
> It turns out that it was indeed a polarity issue.
>
> It looks like that in order to operate properly, I need to setup the
> opposite polarity on HSYNC and VSYNC on the interface. I looked at the
> signals under a scope, and VSYNC is obviously inversed as you
> described. HSYNC, I'm not so sure since the HBLANK period seems very
> long, almost a line.
>
> Since VSYNC at least looks correct, I'd be inclined to think that the
> polarity is inversed on at least the SoC I'm using it on.
>
> Yong, did you test the V3S CSI driver with a parallel interface? With
> what sensor driver? Have you found some polarities issues like this?
Did you try it with Allwinner SoCs?
No. I only tested with a BT1120 signal generated by FPGA or ADV7611. HSYNC
and VSYNC are not used.
For V3s CSI driver, I will add the following to dt-bindings:
Endpoint node properties for CSI1
---------------------------------
- remote-endpoint : (required) a phandle to the bus receiver's endpoint
node
- bus-width: : (required) must be 8, 10, 12 or 16
- pclk-sample : (optional) (default: sample on falling edge)
- hsync-active : (only required for parallel)
- vsync-active : (only required for parallel)
You could try diffrent hsync-active/vsync-active values here.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
Thanks,
Yong
