HSIZE and VSIZE bits 0 to 2 and HSIZE bit 11 are encoded in DSP register
SIZEL.

Signed-off-by: Frank Schäfer <fschaefer....@googlemail.com>
---
 drivers/media/i2c/ov2640.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/media/i2c/ov2640.c b/drivers/media/i2c/ov2640.c
index 11f1b807c292..6f0cc722477d 100644
--- a/drivers/media/i2c/ov2640.c
+++ b/drivers/media/i2c/ov2640.c
@@ -500,6 +500,9 @@ static const struct regval_list ov2640_init_regs[] = {
 static const struct regval_list ov2640_size_change_preamble_regs[] = {
        { BANK_SEL, BANK_SEL_DSP },
        { RESET, RESET_DVP },
+       { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) |
+                SIZEL_HSIZE8_SET(UXGA_WIDTH) |
+                SIZEL_VSIZE8_SET(UXGA_HEIGHT) },
        { HSIZE8, HSIZE8_SET(UXGA_WIDTH) },
        { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) },
        { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
-- 
2.12.2

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