[PATCH v10 40/40] KVM: selftests: arm64: Add GCS registers to get-reg-list

[Mark Brown]

GCS adds new registers GCSCR_EL1, GCSCRE0_EL1, GCSPR_EL1 and GCSPR_EL0. Add
these to those validated by get-reg-list.

Signed-off-by: Mark Brown <broo...@kernel.org>
---
 tools/testing/selftests/kvm/aarch64/get-reg-list.c | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c 
b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
index 709d7d721760..9785f41e6042 100644
--- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c
+++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
@@ -29,6 +29,24 @@ static struct feature_id_reg feat_id_regs[] = {
                0,
                1
        },
+       {
+               ARM64_SYS_REG(3, 0, 2, 5, 0),   /* GCSCR_EL1 */
+               ARM64_SYS_REG(3, 0, 0, 4, 1),   /* ID_AA64PFR1_EL1 */
+               44,
+               1
+       },
+       {
+               ARM64_SYS_REG(3, 0, 2, 5, 1),   /* GCSPR_EL1 */
+               ARM64_SYS_REG(3, 0, 0, 4, 1),   /* ID_AA64PFR1_EL1 */
+               44,
+               1
+       },
+       {
+               ARM64_SYS_REG(3, 0, 2, 5, 2),   /* GCSCRE0_EL1 */
+               ARM64_SYS_REG(3, 0, 0, 4, 1),   /* ID_AA64PFR1_EL1 */
+               44,
+               1
+       },
        {
                ARM64_SYS_REG(3, 0, 10, 2, 2),  /* PIRE0_EL1 */
                ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
@@ -40,6 +58,12 @@ static struct feature_id_reg feat_id_regs[] = {
                ARM64_SYS_REG(3, 0, 0, 7, 3),   /* ID_AA64MMFR3_EL1 */
                4,
                1
+       },
+       {
+               ARM64_SYS_REG(3, 3, 2, 5, 1),   /* GCSPR_EL0 */
+               ARM64_SYS_REG(3, 0, 0, 4, 1),   /* ID_AA64PFR1_EL1 */
+               44,
+               1
        }
 };
 
@@ -460,6 +484,9 @@ static __u64 base_regs[] = {
        ARM64_SYS_REG(3, 0, 2, 0, 1),   /* TTBR1_EL1 */
        ARM64_SYS_REG(3, 0, 2, 0, 2),   /* TCR_EL1 */
        ARM64_SYS_REG(3, 0, 2, 0, 3),   /* TCR2_EL1 */
+       ARM64_SYS_REG(3, 0, 2, 5, 0),   /* GCSCR_EL1 */
+       ARM64_SYS_REG(3, 0, 2, 5, 1),   /* GCSPR_EL1 */
+       ARM64_SYS_REG(3, 0, 2, 5, 2),   /* GCSCRE0_EL1 */
        ARM64_SYS_REG(3, 0, 5, 1, 0),   /* AFSR0_EL1 */
        ARM64_SYS_REG(3, 0, 5, 1, 1),   /* AFSR1_EL1 */
        ARM64_SYS_REG(3, 0, 5, 2, 0),   /* ESR_EL1 */
@@ -475,6 +502,7 @@ static __u64 base_regs[] = {
        ARM64_SYS_REG(3, 0, 13, 0, 4),  /* TPIDR_EL1 */
        ARM64_SYS_REG(3, 0, 14, 1, 0),  /* CNTKCTL_EL1 */
        ARM64_SYS_REG(3, 2, 0, 0, 0),   /* CSSELR_EL1 */
+       ARM64_SYS_REG(3, 3, 2, 5, 1),   /* GCSPR_EL0 */
        ARM64_SYS_REG(3, 3, 13, 0, 2),  /* TPIDR_EL0 */
        ARM64_SYS_REG(3, 3, 13, 0, 3),  /* TPIDRRO_EL0 */
        ARM64_SYS_REG(3, 3, 14, 0, 1),  /* CNTPCT_EL0 */

-- 
2.39.2