On Wed, Nov 08, 2023 at 10:29:47AM -0800, Xin Li wrote: >Add FRED MSRs to the valid passthrough MSR list and disable intercepting >FRED MSRs only if FRED is enumerated after set CPUID. > >Tested-by: Shan Kang <shan.k...@intel.com> >Signed-off-by: Xin Li <xin3...@intel.com> >--- > arch/x86/kvm/vmx/vmx.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > >diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c >index 5d4786812664..327e052d90c1 100644 >--- a/arch/x86/kvm/vmx/vmx.c >+++ b/arch/x86/kvm/vmx/vmx.c >@@ -700,6 +700,9 @@ static bool is_valid_passthrough_msr(u32 msr) > case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8: > /* LBR MSRs. These are handled in > vmx_update_intercept_for_lbr_msrs() */ > return true; >+ case MSR_IA32_FRED_RSP0 ... MSR_IA32_FRED_CONFIG: >+ /* FRED MSRs should be passthrough to FRED guests only */ >+ return true; > } > > r = possible_passthrough_msr_slot(msr) != -ENOENT; >@@ -7813,6 +7816,16 @@ static void vmx_vcpu_config_fred_after_set_cpuid(struct >kvm_vcpu *vcpu) > secondary_vm_exit_controls_setbit(vmx, > SECONDARY_VM_EXIT_SAVE_IA32_FRED | > SECONDARY_VM_EXIT_LOAD_IA32_FRED); >+ >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP0, MSR_TYPE_RW); >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP1, MSR_TYPE_RW); >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP2, MSR_TYPE_RW); >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP3, MSR_TYPE_RW); >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_STKLVLS, MSR_TYPE_RW); >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP1, MSR_TYPE_RW); >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP2, MSR_TYPE_RW); >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP3, MSR_TYPE_RW); >+ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_FRED_CONFIG, MSR_TYPE_RW);
this has the same issue as patch 6.
