Hi, i have an additional question regarding the Open Drain setting. The register is currently impelemented as a read/write register which means the pin mode is configurable by software to Push Pull or Open Drain.
There is also the possiblity (normal way) that the HW (FPGA) configures each pin to the correct mode. Is there actually a way to set an output mode from userland or by the gpio API? I did not find anything about that. If there is no way, i will implement it without software control. I just read out the mode configuration and handle the pins as PP or Open Drain. Regards Andy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
