On Mon, 28 Sep 2015, Dave Hansen wrote: > From: Dave Hansen <dave.han...@linux.intel.com> > > There is an XSAVE state component for Intel Processor Trace. But, > we do not use it and do not expect to ever use it. > > We add a placeholder in the code for it so it is not a mystery and > also so we do not need an explicit enum initialization for Protection > Keys in a moment. > > Why will we never use it? According to Andi Kleen: > > The XSAVE support assumes that there is a single buffer > for each thread. But perf generally doesn't work this > way, it usually has only a single perf event per CPU per > user, and when tracing multiple threads on that CPU it > inherits perf event buffers between different threads. So > XSAVE per thread cannot handle this inheritance case > directly. > > Using multiple XSAVE areas (another one per perf event) > would defeat some of the state caching that the CPUs do. > > Signed-off-by: Dave Hansen <dave.han...@linux.intel.com>
Reviewed-by: Thomas Gleixner <t...@linutronix.de> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
