B4420 has 1 DSP cluster, having 2 DSP cores (SC3900), and a shared L2 cache.
Signed-off-by: Shaveta Leekha <shav...@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com>
---
- based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
branch master
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 6 ++++++
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 23 +++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index f996cce..02fa374 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -94,4 +94,10 @@
reg = <0xc20000 0x40000>;
next-level-cache = <&cpc>;
};
+
+ L2_2: l2-cache-controller@c60000 {
+ compatible = "fsl,b4420-l2-cache-controller";
+ reg = <0xc60000 0x40000>;
+ next-level-cache = <&cpc>;
+ };
};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 4257a77..900086b 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -76,4 +76,27 @@
fsl,portid-mapping = <0x80000000>;
};
};
+
+ dsp-clusters {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsp-cluster0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,sc3900-cluster";
+ reg = <0>;
+
+ dsp0: dsp@0 {
+ compatible = "fsl,sc3900";
+ reg = <0>;
+ next-level-cache = <&L2_2>;
+ };
+ dsp1: dsp@1 {
+ compatible = "fsl,sc3900";
+ reg = <1>;
+ next-level-cache = <&L2_2>;
+ };
+ };
+ };
};
--
1.9.1
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