Marc,
thanks for your quick review.
On 13.08.15 16:11:15, Marc Zyngier wrote:
> On 13/08/15 15:47, Robert Richter wrote:
> > From: Robert Richter <rrich...@cavium.com>
> > static const struct gic_capabilities gicv3_errata[] = {
> > {
> > + .desc = "GIC: Cavium erratum 23154",
> > + .iidr = 0xa100034c, /* ThunderX pass 1.x */
> > + .iidr_mask = 0xffff0fff,
> > + .init = gicv3_enable_cavium_thunderx,
> > + },
>
> I'm even more puzzled. You're working around a CPU bug based on the ITS
> ID registers? Or have you swapped the detection methods for the two errata?
:/ Right, I mixed this up... Must have starred on this for too long.
Will fix that.
Wrt midr: Originally this was written to support iidr. I wanted to
keep the version check in the driver of the hw, an implementation
outside of drivers/irqchip looked not appropriate here as it would
rely then on arch arm64 only. This is the main reason. Apart from
that, I think an implmentation based on struct arm64_cpu_capabilities,
etc. would require much rework compared to my current easy
implementation, e.g:
* binding flags to callbacks and actually run them,
* handing over private driver data (base addr for iidr detection) to
a capabilty's match function.
Overall this looked bloated. Now, that the MIDR also needs to be
checked, it looked better to me to keep the gic hw detection at a
single location in the driver. This also allows us to check a
combination of midr and iidr values.
I hope this sounds reasonable?
-Robert
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