Commit-ID:  b83ff1c8617aac03a1cf807aafa848fe0f0908f2
Gitweb:     http://git.kernel.org/tip/b83ff1c8617aac03a1cf807aafa848fe0f0908f2
Author:     Andi Kleen <[email protected]>
AuthorDate: Sun, 10 May 2015 12:22:41 -0700
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 4 Aug 2015 10:16:56 +0200

x86: Add new MSRs and MSR bits used for Intel Skylake PMU support

Add new MSRs (LBR_INFO) and some new MSR bits used by the Intel Skylake
PMU driver.

Signed-off-by: Andi Kleen <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Link: 
http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
---
 arch/x86/include/asm/msr-index.h  | 6 ++++++
 arch/x86/include/asm/perf_event.h | 7 +++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index c665d34..fcd17c1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -73,6 +73,12 @@
 #define MSR_LBR_CORE_FROM              0x00000040
 #define MSR_LBR_CORE_TO                        0x00000060
 
+#define MSR_LBR_INFO_0                 0x00000dc0 /* ... 0xddf for _31 */
+#define LBR_INFO_MISPRED               BIT_ULL(63)
+#define LBR_INFO_IN_TX                 BIT_ULL(62)
+#define LBR_INFO_ABORT                 BIT_ULL(61)
+#define LBR_INFO_CYCLES                        0xffff
+
 #define MSR_IA32_PEBS_ENABLE           0x000003f1
 #define MSR_IA32_DS_AREA               0x00000600
 #define MSR_IA32_PERF_CAPABILITIES     0x00000345
diff --git a/arch/x86/include/asm/perf_event.h 
b/arch/x86/include/asm/perf_event.h
index dc0f6ed..7bcb861 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -159,6 +159,13 @@ struct x86_pmu_capability {
  */
 #define INTEL_PMC_IDX_FIXED_BTS                                
(INTEL_PMC_IDX_FIXED + 16)
 
+#define GLOBAL_STATUS_COND_CHG                         BIT_ULL(63)
+#define GLOBAL_STATUS_BUFFER_OVF                       BIT_ULL(62)
+#define GLOBAL_STATUS_UNC_OVF                          BIT_ULL(61)
+#define GLOBAL_STATUS_ASIF                             BIT_ULL(60)
+#define GLOBAL_STATUS_COUNTERS_FROZEN                  BIT_ULL(59)
+#define GLOBAL_STATUS_LBRS_FROZEN                      BIT_ULL(58)
+
 /*
  * IBS cpuid feature detection
  */
--
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