On 07/25/2015 02:21 AM, Moritz Fischer wrote: > This adds a reset controller driver to control the Xilinx Zynq > SoC's various resets. > > Signed-off-by: Moritz Fischer <[email protected]> > --- > drivers/reset/Makefile | 1 + > drivers/reset/reset-zynq.c | 142 > +++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 143 insertions(+) > create mode 100644 drivers/reset/reset-zynq.c > > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 157d421..3fe50e7 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o > obj-$(CONFIG_ARCH_STI) += sti/ > +obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o > diff --git a/drivers/reset/reset-zynq.c b/drivers/reset/reset-zynq.c > new file mode 100644 > index 0000000..05e37f8 > --- /dev/null > +++ b/drivers/reset/reset-zynq.c > @@ -0,0 +1,142 @@ > +/* > + * Copyright (c) 2015, National Instruments Corp. > + * > + * Xilinx Zynq Reset controller driver > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/mfd/syscon.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/reset-controller.h> > +#include <linux/regmap.h> > +#include <linux/types.h> > + > +/* Offsets into SLCR regmap */ > +#define SLCR_RST_CTRL_OFFSET 0x200 /* FPGA Software Reset Control */ > + > +#define NBANKS 18 > + > +struct zynq_reset_data { > + struct regmap *slcr; > + struct reset_controller_dev rcdev; > +}; > + > +#define to_zynq_reset_data(p) \ > + container_of((p), struct zynq_reset_data, rcdev) > + > +static int zynq_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); > + > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > +
Personally me I would also add debug message here to be simply enabled
for easier tracking.
> + regmap_update_bits(priv->slcr,
> + SLCR_RST_CTRL_OFFSET + (bank * 4),
> + BIT(offset),
> + BIT(offset));
> +
> + return 0;
> +}
> +
> +static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
> +
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> +
debug message here too.
> + regmap_update_bits(priv->slcr,
> + SLCR_RST_CTRL_OFFSET + (bank * 4),
> + BIT(offset),
> + ~BIT(offset));
> +
> + return 0;
> +}
> +
> +static int zynq_reset_status(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
> +
> + int bank = id / BITS_PER_LONG;
> + int offset = id % BITS_PER_LONG;
> + u32 reg;
> +
> + regmap_read(priv->slcr, SLCR_RST_CTRL_OFFSET + (bank * 4), ®);
debug message here too.
> +
> + return !(reg & BIT(offset));
> +}
> +
> +static const struct reset_control_ops zynq_reset_ops = {
Remove const here - there is sparse warning.
> + .assert = zynq_reset_assert,
> + .deassert = zynq_reset_deassert,
> + .status = zynq_reset_status,
> +};
> +
> +static int zynq_reset_probe(struct platform_device *pdev)
> +{
> + struct zynq_reset_data *priv;
> +
> + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> + platform_set_drvdata(pdev, priv);
> +
> + priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> + "syscon");
> + if (IS_ERR(priv->slcr)) {
> + dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
> + return PTR_ERR(priv->slcr);
> + }
> +
> + priv->rcdev.owner = THIS_MODULE;
> + priv->rcdev.nr_resets = NBANKS * BITS_PER_LONG;
> + priv->rcdev.ops = &zynq_reset_ops;
> + priv->rcdev.of_node = pdev->dev.of_node;
> + reset_controller_register(&priv->rcdev);
> +
> + return 0;
> +}
> +
> +static int zynq_reset_remove(struct platform_device *pdev)
> +{
> + struct zynq_reset_data *priv = platform_get_drvdata(pdev);
> +
> + reset_controller_unregister(&priv->rcdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id zynq_reset_dt_ids[] = {
> + { .compatible = "xlnx,zynq-reset", },
> + { /* sentinel */ },
> +};
> +
> +static struct platform_driver zynq_reset_driver = {
> + .probe = zynq_reset_probe,
> + .remove = zynq_reset_remove,
> + .driver = {
> + .name = "zynq-pl-reset",
> + .of_match_table = zynq_reset_dt_ids,
> + },
> +};
> +module_platform_driver(zynq_reset_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Moritz Fischer <[email protected]>");
> +MODULE_DESCRIPTION("Zynq Reset Controller Driver");
>
Also I am missing enabling reset controller in the arch.
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 78e5e007f52d..02a84fdee1bd 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,6 +1,7 @@
config ARCH_ZYNQ
bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
select ARCH_SUPPORTS_BIG_ENDIAN
+ select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GIC
select ARM_GLOBAL_TIMER if !CPU_FREQ
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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