Maciej W. Rozycki wrote:
Well, Intel's "Multiprocessor Specification" mandates that (see section 3.6.1 and also the compliance list in Appendix C). I does not mandate local APIC IDs to be consecutive though.
Unless I am mistaken, the MP spec does not say that _CPUs_ must start from 0. We had an IO-APIC at 0. The MP spec says that the IDs must be unique (I am told this isn't true any more because an IO APIC and a CPU may have the same ID) and _need not_ be consecutive.
We tried different setups; one had IO APICs at 0,1,2 and CPUs starting at 16. I can't see that this is forbidden (the reason is that the IO-APICs have only 4-bit APIC ID registers). Anyway we changed it now to have both IO-APICs and CPUs start at 0.
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