andi, you can see the difference with the patch Booting processor 1/1 rip 6000 rsp ffff810181c61f58 Initializing CPU#1 masked ExtINT on CPU#1 Calibrating delay using timer specific routine.. 4000.31 BogoMIPS (lpj=8000624) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) stepping 0a CPU 1: Syncing TSC to CPU 0. CPU 1: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 886 cycles) Booting processor 2/2 rip 6000 rsp ffff81017ffa3f58 Initializing CPU#2 masked ExtINT on CPU#2 Calibrating delay using timer specific routine.. 4000.30 BogoMIPS (lpj=8000605) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) stepping 0a CPU 2: Syncing TSC to CPU 0. CPU 2: synchronized TSC with CPU 0 (last diff 1 cycles, maxerr 901 cycles) Booting processor 3/3 rip 6000 rsp ffff8101fffa9f58 Initializing CPU#3 masked ExtINT on CPU#3 Calibrating delay using timer specific routine.. 4000.31 BogoMIPS (lpj=8000622) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) stepping 0a CPU 3: Syncing TSC to CPU 0. CPU 3: synchronized TSC with CPU 0 (last diff -3 cycles, maxerr 1504 cycles) Brought up 4 CPUs
without the patch Booting processor 1/4 APIC 0x1 Initializing CPU#1 masked ExtINT on CPU#1 Calibrating delay using timer specific routine.. 4000.30 BogoMIPS (lpj=8000608) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) CPU 1(1) -> Node 1 -> Core 0 stepping 0a CPU 1: Syncing TSC to CPU 0. Booting processor 2/4 APIC 0x2 Initializing CPU#2 masked ExtINT on CPU#2 CPU 1: synchronized TSC with CPU 0 (last diff 1 cycles, maxerr 893 cycles) Calibrating delay using timer specific routine.. 4000.36 BogoMIPS (lpj=8000724) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) CPU 2(1) -> Node 2 -> Core 0 stepping 0a CPU 2: Syncing TSC to CPU 0. Booting processor 3/4 APIC 0x3 Initializing CPU#3 masked ExtINT on CPU#3 CPU 2: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 904 cycles) Calibrating delay using timer specific routine.. 4000.16 BogoMIPS (lpj=8000335) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) CPU 3(1) -> Node 3 -> Core 0 stepping 0a CPU 3: Syncing TSC to CPU 0. Brought up 4 CPUs time.c: Using PIT/TSC based timekeeping. testing NMI watchdog ... OK. checking if image is initramfs...<6>CPU 3: synchronized TSC with CPU 0 (last diff -18 cycles, maxerr 1504 cycles) it isn't (no cpio magic); looks like an initrd So my patch still can be used with Eric's, It just serialize the TSC_SYNC between cpu. I wonder it you can refine to make TSC_SYNC serialize that beteen CPU. That will make CPU X:synchronized TSC ... in fixed postion and timming. YH On 8/10/05, Andi Kleen <[EMAIL PROTECTED]> wrote: > On Wed, Aug 10, 2005 at 04:14:19PM -0700, Mike Waychison wrote: > > YhLu wrote: > > >andi, > > > > > >please refer the patch, it will move cpu_set(, cpu_callin_map) from > > >smi_callin to start_secondary. > > > > > > This patch fixes an apparent race / lockup on our 2-way dual cores (when > > applied against 2.6.12.3). The machine was locking up after > > "Initializing CPU#2". > > The real solution for this issue is the smp_call_function_single patch from > Eric > that I reposted yesterday. Yh's patch just changed the timing slightly. > > > -Andi > - > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to [EMAIL PROTECTED] > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ > - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
