> -----Original Message----- > From: ble...@google.com [mailto:ble...@google.com] On Behalf Of Benson > Leung > Sent: Friday, May 15, 2015 3:37 AM > To: Rhyland Klein > Cc: Peter De Schrijver; Mike Turquette; Stephen Warren; Stephen Boyd; Thierry > Reding; Alexandre Courbot; Bill Huang; Paul Walmsley; Jim Lin; linux- > c...@vger.kernel.org; linux-te...@vger.kernel.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic > > On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rkl...@nvidia.com> wrote: > > From: Bill Huang <bilhu...@nvidia.com> > > > > Super clock divider control and clock source mux of Tegra210 has > > changed a little against prior SoCs, this patch adds Gen5 logic to > > address those differences. > > > > Signed-off-by: Bill Huang <bilhu...@nvidia.com> > > --- > > v2: > > - Fixed sclk divider address (0x370 -> 0x2c) > > > > drivers/clk/tegra/Makefile | 1 + > > drivers/clk/tegra/clk-tegra-super-gen5.c | 150 > ++++++++++++++++++++++++++++++ > > drivers/clk/tegra/clk.h | 3 + > > 3 files changed, 154 insertions(+) > > create mode 100644 drivers/clk/tegra/clk-tegra-super-gen5.c > > I've diffed clk-tegra-super-gen5.c and the existing clk-tegra-super-gen4.c, > and > there's a lot of code duplication here. > They're the same pair of functions, with several small changes. Since the idea > behind pulling out the super clock initialization into a common file was to > reuse > the same init, could we extend the super-gen4 file (rename if you have to) to > support both gens instead? > Thanks, we'll integrate gen5 into gen4 file in v6. > -- > Benson Leung > Software Engineer, Chrom* OS > ble...@chromium.org
