On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rkl...@nvidia.com> wrote: > From: Bill Huang <bilhu...@nvidia.com> > > Super clock divider control and clock source mux of Tegra210 has changed > a little against prior SoCs, this patch adds Gen5 logic to address those > differences. > > Signed-off-by: Bill Huang <bilhu...@nvidia.com>
It looks like Mikko's and Thierry's EMC changes landed since you rebased : 0c1135f clk: tegra: EMC clock driver depends on EMC driver dc9fdb6 clk: tegra: Add EMC clock driver So v5 doesn't apply cleanly anymore. Could you rebase? > --- > v2: > - Fixed sclk divider address (0x370 -> 0x2c) -- Benson Leung Software Engineer, Chrom* OS ble...@chromium.org -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
