* Karsten Wiese <[EMAIL PROTECTED]> wrote:
> Hi,
>
> this should likely be addressed to VIA Taiwan,
> but I don't know their engineer's e-mail address and their forum
> doesn't work for me.
> Maybe somebody here has a clue?
> Or maybe this is even motherboard specific?
>
> To reproduce:
> $ aplay -Dhw:0 -fdat /dev/zero
>
> On a sane system (or here in PIC Mode) you'll see
> around 12 Interrupts/s.
> Here I see 24.
i think this is an effect of the 'POST-flush' symptom: the IO-APIC write
of unmasking the IRQ does not reach the chipset before the ACK via the
local-APIC does. Does it work fine if you artificially read after the
IO-APIC write?
Ingo
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