On Tue, Feb 24, 2015 at 03:16:38PM -0800, Vikas Shivappa wrote:
> This patch adds support for the new Cache Allocation Technology (CAT)
> feature found in future Intel Xeon processors. CAT is part of Intel
> Resource Director Technology(RDT) which enables sharing of processor
> resources. This patch includes CPUID enumeration routines for CAT and
> new values to track CAT resources to the cpuinfo_x86 structure.
>
> Cache Allocation Technology(CAT) provides a way for the Software
> (OS/VMM) to restrict cache allocation to a defined 'subset' of cache
> which may be overlapping with other 'subsets'. This feature is used
> when allocating a line in cache ie when pulling new data into the cache.
> The programming of the h/w is done via programming MSRs.
>
> More information about CAT be found in the Intel (R) x86 Architecture
> Software Developer Manual, section 17.15.
>
> Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>
> ---
> arch/x86/include/asm/cpufeature.h | 6 ++++-
> arch/x86/include/asm/processor.h | 3 +++
> arch/x86/kernel/cpu/Makefile | 1 +
> arch/x86/kernel/cpu/common.c | 15 ++++++++++++
> arch/x86/kernel/cpu/intel_rdt.c | 51
> +++++++++++++++++++++++++++++++++++++++
> init/Kconfig | 11 +++++++++
> 6 files changed, 86 insertions(+), 1 deletion(-)
> create mode 100644 arch/x86/kernel/cpu/intel_rdt.c
>
> diff --git a/arch/x86/include/asm/cpufeature.h
> b/arch/x86/include/asm/cpufeature.h
> index 54fd8eb..d97b785 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -12,7 +12,7 @@
> #include <asm/disabled-features.h>
> #endif
>
> -#define NCAPINTS 13 /* N 32-bit words worth of info */
> +#define NCAPINTS 14 /* N 32-bit words worth of info */
> #define NBUGINTS 1 /* N 32-bit bug flags */
>
> /*
> @@ -227,6 +227,7 @@
> #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional
> Memory */
> #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
> #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection
> Extension */
> +#define X86_FEATURE_RDT ( 9*32+15) /* Resource Allocation */
> #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
> #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
> #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX
> instructions */
> @@ -248,6 +249,9 @@
> /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
> #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if
> 1 */
>
> +/* Intel-defined CPU features, CPUID level 0x00000010:0 (ebx), word 13 */
> +#define X86_FEATURE_CAT_L3 (13*32 + 1) /*Cache QOS Enforcement L3*/
^^^^
Spaces between comment markers and text please.
> +
> /*
> * BUG word(s)
> */
> diff --git a/arch/x86/include/asm/processor.h
> b/arch/x86/include/asm/processor.h
> index 242ceed..81d95ac 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -114,6 +114,9 @@ struct cpuinfo_x86 {
> int x86_cache_occ_scale; /* scale to bytes */
> int x86_power;
> unsigned long loops_per_jiffy;
> + /* Cache Allocation Technology values */
> + int x86_cat_cbmlength;
> + int x86_cat_closs;
Do I see it correctly, those two can be u16 each?
> /* cpuid returned max cores value: */
> u16 x86_max_cores;
> u16 apicid;
> diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
> index 6c1ca13..6c91e39 100644
> --- a/arch/x86/kernel/cpu/Makefile
> +++ b/arch/x86/kernel/cpu/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) +=
> perf_event_intel_uncore.o \
> perf_event_intel_uncore_nhmex.o
> endif
>
> +obj-$(CONFIG_CGROUP_RDT) +=intel_rdt.o
>
> obj-$(CONFIG_X86_MCE) += mcheck/
> obj-$(CONFIG_MTRR) += mtrr/
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 9b0fb70..c5ea1dd 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -668,6 +668,21 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
> }
> }
>
> + /* Additional Intel-defined flags: level 0x00000010 */
> + if (c->cpuid_level >= 0x00000010) {
> + u32 eax, ebx, ecx, edx;
> +
> + cpuid_count(0x00000010, 0, &eax, &ebx, &ecx, &edx);
> + c->x86_capability[13] = ebx;
> +
> + if (cpu_has(c, X86_FEATURE_CAT_L3)) {
> +
> + cpuid_count(0x00000010, 1, &eax, &ebx, &ecx, &edx);
> + c->x86_cat_closs = (edx & 0xffff) + 1;
> + c->x86_cat_cbmlength = (eax & 0xf) + 1;
> + }
> + }
> +
> /* AMD-defined flags: level 0x80000001 */
> xlvl = cpuid_eax(0x80000000);
> c->extended_cpuid_level = xlvl;
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> new file mode 100644
> index 0000000..46ce449
> --- /dev/null
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -0,0 +1,51 @@
> +/*
> + * Resource Director Technology(RDT) code
> + *
> + * Copyright (C) 2014 Intel Corporation
> + *
> + * 2014-09-10 Written by Vikas Shivappa
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * More information about RDT be found in the Intel (R) x86 Architecture
> + * Software Developer Manual, section 17.15.
> + */
> +
> +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> +
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/spinlock.h>
> +
> +static inline bool rdt_supported(struct cpuinfo_x86 *c)
> +{
> + if (cpu_has(c, X86_FEATURE_RDT))
> + return true;
> +
> + return false;
> +}
> +
> +static int __init rdt_late_init(void)
> +{
> + struct cpuinfo_x86 *c = &boot_cpu_data;
> + int maxid, cbm_len;
> +
> + if (!rdt_supported(c))
you can do cpu_has() directly here instead of the custom wrapper and
drop that rdt_supported() thing.
> + return -ENODEV;
> +
> + maxid = c->x86_cat_closs;
> + cbm_len = c->x86_cat_cbmlength;
No need for those local variables, just use c->...
> +
> + pr_info("cbmlength:%u,Closs: %u\n", cbm_len, maxid);
This text message needs to be much more user-friendly if it is going out
to the console unconditionally.
> +
> + return 0;
> +}
> +
> +late_initcall(rdt_late_init);
Btw, this could all fit nicely in arch/x86/kernel/cpu/intel.c AFAICT
instead of adding a separate file and you probably don't even need the
late_initcall() even...
> diff --git a/init/Kconfig b/init/Kconfig
> index 9afb971..c5004b3 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -961,6 +961,17 @@ config CPUSETS
>
> Say N if unsure.
>
> +config CGROUP_RDT
> + bool "Resource Director Technology cgroup subsystem"
> + depends on X86_64
depends on X86_64 && CPU_SUP_INTEL
Also, this should probably also depend on CGROUP-something or so
AFAICT...
> + help
> + This option provides framework to allocate resources like
> + cache lines when applications fill cache.
> + This can be used by users to configure how much cache
> + that can be allocated to different applications.
This help text doesn't really help me if I'm Joe User.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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