On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: > From: Tuomas Tynkkynen <ttynkky...@nvidia.com> > > The DFLL is the main clocksource for the fast CPU cluster on Tegra124 > and also provides automatic CPU rail voltage scaling as well. The DFLL > is a separate IP block from the usual Tegra124 clock-and-reset > controller, so it gets its own node in the device tree. >
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