On Mon, Feb 02, 2015 at 10:20:49AM +0000, Will Deacon wrote: > On Fri, Jan 30, 2015 at 09:55:55PM +0000, Arnd Bergmann wrote: > > - reg = (iova & ~0xfff) >> 32; > > + reg = ((u64)iova & ~0xfff) >> 32; > > writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI); > > } > > Thanks, Arnd. > > Acked-by: Will Deacon <will.dea...@arm.com> > > Joerg, could you pick this one up directly please? I don't have any other > ARM SMMU fixes queued at the moment.
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