Hi, Am 28.01.2015 um 17:10 schrieb Zhi Li: > On Wed, Jan 28, 2015 at 9:52 AM, Stefan Wahren <stefan.wah...@i2se.com> wrote: >> Hi, >> >> Am 28.01.2015 um 04:36 schrieb Zhi Li: >>> On Tue, Jan 27, 2015 at 7:51 PM, Mike Turquette <mturque...@linaro.org> >>> wrote: >>>> Quoting Marek Vasut (2015-01-21 15:39:01) >>>>> On Wednesday, January 21, 2015 at 05:16:03 PM, Zhi Li wrote: >>>>>> On Sun, Dec 28, 2014 at 4:26 AM, Stefan Wahren <stefan.wah...@i2se.com> >>>>>> wrote: >>>>>>> According to i.MX23 and i.MX28 reference manual the fractional >>>>>>> clock control registers must be addressed by byte instructions. >>>>>> I don't think mx23 and mx28 have such limitation. I will double check >>>>>> with IC team about this. >>>>>> RTL is generated from a xml file. All registers implement is unified. >>>>>> I don't think only clock control register have such limitation and >>>>>> other registers not. >>>>> Hi, >>>>> >>>>> Section 10.8.24 in the MX28 datasheet (Fractional Clock Control Register >>>>> 0) >>>>> states otherwise, but maybe the documentation is simply not matching the >>>>> silicon. >>>>> >>>>> Here's a quote: >>>>> " >>>>> This register controls the 9-phase fractional clock dividers. The >>>>> fractional >>>>> clock frequencies are a product of the values in these registers. NOTE: >>>>> This >>>>> register can only be addressed by byte instructions. Addressing word or >>>>> half- >>>>> word are not allowed. >>>>> " >>>>> >>>>> I also recall seeing weird behavior when these registers were accessed by >>>>> word >>>>> access in U-Boot, so I believe the datasheet is correct. >>>> Hi Frank, >>>> >>>> Are you satisfied with this patch? >>> I asked IC designer about this. >>> They will check RTL code. >>> I will check their status again. >>> Our released BSP code used 32bit WORD access. >> i want to point out that the 32bit WORD is divided in 4 parts (IO0FRAC, >> IO1FRAC, EMIFRAC, CPUFRAC). Yes, it's true that BSP code access the >> register as 32bit, but it's never modify the complete 32bit at once just >> only 1 part (8bit) at a time. >> >> So here is my theory about Fractional Clock Control Register: >> >> Reading as 32bit WORD => safe >> Modify only 1 part (8bit) of the 32bit WORD => safe >> Modify more than 1 part of the 32bit WORD => unsafe !!! > Yes, it is align with what I get from IC designer. > > best regards > Frank Li
okay, fine. The clk init for the i.MX28 in the kernel tries to the set IO0FRAC and IO1FRAC at once. So this patch fix this problem. And since i was on that, i changed all accesses on that register to 8bit to avoid this problem in the future. So what's your opinion about this patch? Best regards Stefan > >> Best regards >> Stefan >> >>> best regards >>> Frank Li >>>> Regards, >>>> Mike >>>> >>>>> Best regards, >>>>> Marek Vasut >> > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
