BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC. To
avoid possible coherency problems, flush the RAC upon DMA completion.
Signed-off-by: Kevin Cernekee <cerne...@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.s...@gmail.com>
---
arch/mips/mm/dma-default.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index af5f046..38ee47a 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -18,6 +18,7 @@
#include <linux/highmem.h>
#include <linux/dma-contiguous.h>
+#include <asm/bmips.h>
#include <asm/cache.h>
#include <asm/cpu-type.h>
#include <asm/io.h>
@@ -69,6 +70,20 @@ static inline struct page *dma_addr_to_page(struct device
*dev,
*/
static inline int cpu_needs_post_dma_flush(struct device *dev)
{
+ if (boot_cpu_type() == CPU_BMIPS3300 ||
+ boot_cpu_type() == CPU_BMIPS4350 ||
+ boot_cpu_type() == CPU_BMIPS4380) {
+ void __iomem *cbr = BMIPS_GET_CBR();
+ u32 cfg;
+
+ /* Flush stale data out of the readahead cache */
+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+ __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
+ __raw_readl(cbr + BMIPS_RAC_CONFIG);
+
+ return 0;
+ }
+
return !plat_device_is_coherent(dev) &&
(boot_cpu_type() == CPU_R10000 ||
boot_cpu_type() == CPU_R12000 ||
--
2.1.1
--
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