> + /*
> + * This controller does not give completion interrupt after a
> + * master receive transfer if HOLD bit is set (repeated start),
> + * resulting in SW timeout. Hence, if a receive transfer is
> + * followed by any other transfer, an error is returned
> + * indicating that this sequence is not supported.
> + */
> + for (count = 0; count < num-1; count++) {
> + if (msgs[count].flags & I2C_M_RD)
> + return -EOPNOTSUPP;
> + }Yeah, a lot better. Probably it would be good to inform the user with a warning what went wrong?
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