Hi Magnus,

On Thu, Dec 4, 2014 at 8:33 AM, Magnus Damm <magnus.d...@gmail.com> wrote:
>>> --- 0002/arch/arm/boot/dts/r8a7779.dtsi
>>> +++ work/arch/arm/boot/dts/r8a7779.dtsi       2014-12-03 20:27:49.000000000 
>>> +0900
>>> @@ -139,7 +139,7 @@
>>>               interrupt-controller;
>>>       };
>>>
>>> -     irqpin0: irqpin@fe780010 {
>>> +     irqpin0: irqpin@fe780000 {
>>>               compatible = "renesas,intc-irqpin-r8a7779", 
>>> "renesas,intc-irqpin";
>>>               #interrupt-cells = <2>;
>>>               status = "disabled";
>>> @@ -148,7 +148,8 @@
>>>                       <0xfe780010 4>,
>>>                       <0xfe780024 4>,
>>>                       <0xfe780044 4>,
>>> -                     <0xfe780064 4>;
>>> +                     <0xfe780064 4>,
>>> +                     <0xfe780000 4>;
>>
>> Is there any order implied by the above list?
>> Naïvely I would expect it to be sorted numerically.
>
> Yes, the driver assumes the register banks to be passed in a certain
> order. In the case of r8a7779 we add one more register bank at the end
> for IRLM setup. Register detail (base address, access size, order and
> bitfield width) varies with SoC version. So the IRLM register will be
> at different addresses depending on SoC, but the driver wants it at
> the end of the list.

As these are all individual registers, and there are that many, I think
it's worth adding a reg-names property to identify the registers.
Of course the driver still has to support the old anonymous order
for backwards compatibility.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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