On 2014/11/18 21:33, Yun Wu (Abel) wrote:
> On 2014/11/18 18:19, Thomas Gleixner wrote:
>
>> On Tue, 18 Nov 2014, Yun Wu (Abel) wrote:
>>> On 2014/11/12 21:43, Thomas Gleixner wrote:
>>>> struct irq_chip {
>>>> @@ -359,6 +360,7 @@ struct irq_chip {
>>>> void (*irq_release_resources)(struct irq_data *data);
>>>>
>>>> void (*irq_compose_msi_msg)(struct irq_data *data, struct
>>>> msi_msg *msg);
>>>> + void (*irq_write_msi_msg)(struct irq_data *data, struct
>>>> msi_msg *msg);
>>>
>>> Hmm... It's really weird.
>>> I don't think it's the interrupt controllers' responsibility to write
>>> messages
>>> for all the endpoint devices since the methods of configuring message
>>> registers
>>> may different between these devices. And theoretically, the endpoint devices
>>> themselves should take the responsibility to configure their message
>>> registers.
>>> To say the least, the write_msg callback here still need to call some
>>> certain
>>> interfaces provided by the corresponding device.
>>>
>>> There would be lots of ARM new devices capable of sending message
>>> based interrupts to interrupt controllers, does all the drivers of
>>> the devices need to expose a write_msg callback to interrupt
>>> controllers?
>>
>> Well, writing the message _IS_ part of the interrupt controller.
>>
>> So in order to enable non PCI based MSI we want to have generic
>> infrastructure with minimal per device/device class callbacks and of
>> course you need to provide that callback for your special device.
>>
>> We already have non PCI based MSI controllers in x86 today and we need
>> to handle the whole stuff with tons of copied coded extra for each of
>> those. So consolidating it into common infrastructure allows us to get
>> rid of the pointless copied code and reduce the per device effort to
>> the relevant hardware specific callbacks. irq_write_msi_msg being one
>> of those.
>>
>
> At least, we have the same goal.
> I will illustrate my thoughts by an example.
> The current code is something like:
>
> Device A
> ========
> void A_write_msg() { ... }
>
> Group B
> (a group of devices behave same on writing messages, i.e. PCI)
> =======
> void B_write_msg() { ... }
>
> Controller
> ==========
> irq_chip.irq_write_msi_msg () {
> if (A)
> A_write_msg();
> if (B)
> B_write_msg();
> }
>
> It's horrible when new devices come out, since we need to modify the
> controller part for each new device.
> What I suggested is:
>
> MSI Core
> ========
> struct msi_ops { .write_msg, };
> struct msi_desc { .msi_ops, };
>
> write_msg() {
> X = get_dev();
> irq_chip.compose_msg(X); // IRQ chips' responsibility
> X_msi_ops.write_msg(); // nothing to do with IRQ chips
> }
>
> Device A
> ========
> void A_write_msg() { ... }
> A_msi_ops.write_msg = A_write_msg;
>
> Group B
> =======
> void B_write_msg() { ... }
> B_msi_ops.write_msg = B_write_msg;
>
> Please correct me if I misunderstood anything.
Please take a look at following file, which uses the common MSI
framework to support PCI, DMAR and HPET interrupt on x86.
https://github.com/jiangliu/linux/blob/irqdomain/p2v7/arch/x86/kernel/apic/msi.c
Regards!
Gerry
>
> Thanks,
> Abel
>
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