On Fri, Nov 07, 2014 at 07:44:16AM +0100, Michal Simek wrote: > On 11/06/2014 06:22 PM, Andreas Färber wrote: > > The Parallella board comes with a U-Boot bootloader that loads one of > > two predefined FPGA bitstreams before booting the kernel. Both define an > > AXI interface to the on-board Epiphany processor. > > > > Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. > > > > Otherwise accessing, e.g., the ESYSRESET register freezes the board, > > as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. > > > > Cc: <sta...@vger.kernel.org> # 3.17.x > > Signed-off-by: Andreas Färber <afaer...@suse.de> > > --- > > Michal/Olof, please consider this trivial patch as a fix for 3.18. > > Acked-by: Michal Simek <michal.si...@xilinx.com> > > Olof, Arnd: Can you please pick this directly?
Done, applied to fixes. -Olof -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
