On 09/03/14 10:00, Sudeep Holla wrote: > From: Sudeep Holla <[email protected]> > > This patch adds support for cacheinfo on ARM platforms. > > On ARMv7, the cache hierarchy can be identified through Cache Level ID > register(CLIDR) while the cache geometry is provided by Cache Size ID > register(CCSIDR). > > On architecture versions before ARMv7, CLIDR and CCSIDR is not > implemented. The cache type register(CTR) provides both cache hierarchy > and geometry if implemented. For implementations that doesn't support > CTR, we need to list the probable value of CTR if it was implemented > along with the cpuid for the sake of simplicity to handle them. > > Since the architecture doesn't provide any way of detecting the cpus > sharing particular cache, device tree is used fo the same purpose. > On non-DT platforms, first level caches are per-cpu while higher level > caches are assumed system-wide. > > Signed-off-by: Sudeep Holla <[email protected]> > Cc: Russell King <[email protected]> > Cc: Will Deacon <[email protected]> > Cc: [email protected] >
Tested-by: Stephen Boyd <[email protected]> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
