Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.w...@freescale.com>
---
arch/arm/mach-imx/clk-imx6q.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index d5bf1e2..013d3cd 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -108,6 +108,9 @@ static struct clk_div_table video_div_table[] = {
static unsigned int share_count_esai;
static unsigned int share_count_asrc;
+static unsigned int share_count_ssi1;
+static unsigned int share_count_ssi2;
+static unsigned int share_count_ssi3;
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
@@ -392,9 +395,12 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb",
base + 0x7c, 6);
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg",
base + 0x7c, 12);
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif",
"spdif_podf", base + 0x7c, 14);
- clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg",
base + 0x7c, 18);
- clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg",
base + 0x7c, 20);
- clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg",
base + 0x7c, 22);
+ clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg",
"ipg", base + 0x7c, 18, &share_count_ssi1);
+ clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg",
"ipg", base + 0x7c, 20, &share_count_ssi2);
+ clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg",
"ipg", base + 0x7c, 22, &share_count_ssi3);
+ clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1",
"ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
+ clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2",
"ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
+ clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3",
"ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg",
base + 0x7c, 24);
clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial",
"uart_serial_podf", base + 0x7c, 26);
clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg",
base + 0x80, 0);
--
1.7.9.5
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