Since the Flextimer device will be implemented in BE mode on
LS1 SoC, and in LE mode on Vybrid, LS2 SoCs, so here we need
the endianness judgment before doing the mmio.
Signed-off-by: Xiubo Li <li.xi...@freescale.com>
Signed-off-by: Jingchang Lu <jingchang...@freescale.com>
---
drivers/clocksource/fsl_ftm_timer.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/fsl_ftm_timer.c
b/drivers/clocksource/fsl_ftm_timer.c
index 13222c1..c4d23d0f 100644
--- a/drivers/clocksource/fsl_ftm_timer.c
+++ b/drivers/clocksource/fsl_ftm_timer.c
@@ -226,6 +226,11 @@ static int __init ftm_clockevent_init(unsigned long freq,
int irq)
return 0;
}
+static cycle_t ftm_clocksource_read_up(struct clocksource *c)
+{
+ return ftm_readl(clksrc_base + FTM_CNT) & 0xffff;
+}
+
static int __init ftm_clocksource_init(unsigned long freq)
{
int err;
@@ -238,7 +243,7 @@ static int __init ftm_clocksource_init(unsigned long freq)
sched_clock_register(ftm_read_sched_clock, 16, freq / (1 << priv->ps));
err = clocksource_mmio_init(priv->clksrc_base + FTM_CNT, "fsl-ftm",
freq / (1 << priv->ps), 300, 16,
- clocksource_mmio_readl_up);
+ ftm_clocksource_read_up);
if (err) {
pr_err("ftm: init clock source mmio failed: %d\n", err);
return err;
--
1.8.5
--
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