This is where we describe the different new and generic options used by the ST BCH driver.
Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> --- Documentation/devicetree/bindings/mtd/stm-nand.txt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/stm-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/stm-nand.txt b/Documentation/devicetree/bindings/mtd/stm-nand.txt new file mode 100644 index 0000000..3176252 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/stm-nand.txt @@ -0,0 +1,74 @@ +STM BCH NAND Support +-------------------- + +Required properties: + +- compatible : Should be "st,nand-bch" +- reg : Should contain register's location and length +- reg-names : "nand_mem" - NAND Controller register map + "nand_dma" - BCH Controller DMA configuration map +- interrupts : Interrupt number +- interrupt-names : "nand_irq" - NAND Controller IRQ +- st,nand-banks : Subnode representing one or more "banks" of NAND + Flash, connected to an STM NAND Controller (see + description below). +- nand-ecc-strength : Generic NAND property (See mtd/nand.txt) + Options are; 0, 18 or 30. If not present, the driver + will choose the strongest scheme compatible if the + OOB size. + +Properties describing Bank of NAND Flash ("st,nand-banks"): + +- st,nand-csn : Chip select associated with the Bank. + +- st,nand-timing-relax : [Optional] Number of IP clock cycles by which to + "relax" timing configuration. Required on some boards + to accommodate board-level limitations. Applies to + ONFI timing mode configuration. + +- nand-on-flash-bbt : Generic NAND property (See mtd/nand.txt) + +- partitions : [Optional] Subnode describing MTD partition map + (see mtd/partition.txt) + +Note, during initialisation, the NAND Controller timing registers are configured +according to one of the following methods, in order of precedence: + + 1. Configuration based on ONFI timing mode, as advertised by the + device during ONFI-probing (ONFI-compliant NAND only). + + 2. Use reset/safe timing values + +Example: + + nand@fe901000 { + compatible = "st,nand-bch"; + reg = <0xfe901000 0x1000>, <0xfef00800 0x0800>; + reg-names = "nand_mem", "nand_dma"; + interrupts = <0 139 0x0>; + interrupt-names = "nand_irq"; + nand-ecc-strength = <30>; + + status = "okay"; + + bank0 { + /* NAND_BBT_USE_FLASH */ + nand-on-flash-bbt; + st,nand-csn = <0>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + + partition@0{ + label = "NANDFlash1"; + reg = <0x00000000 0x00800000>; + }; + + partition@800000{ + label = "NANDFlash2"; + reg = <0x00800000 0x0f800000>; + }; + }; + }; + }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
