On Thu, 31 Jul 2014, Thomas Gleixner wrote:
> On Wed, 30 Jul 2014, Rafael J. Wysocki wrote:
> Before this code changes in any way I want to see:
>
> 1) a description of the existing semantics and their background
>
> 2) a description of the short comings of the existing semantics w/o
> considering the new fangled (hardware) use cases
>
> 3) a description how to mitigate the short comings described in #2
> w/o breaking the world and some more and introducing hard to
> decode regressions
>
> 4) a description why the improvements introduced by #3 are not
> sufficient for the new fangled (hardware) use cases
>
> 5) a description how to mitigate the short comings described in #4
> w/o breaking the world and some more and introducing hard to
> decode regressions
Aside of that I want to see a coherent explanation why a shared MSI
interrupt makes any sense at all.
25: 1 <....> 0 PCI-MSI-edge aerdrv, PCIe PME
AFAICT, that's the primary reason why you insist to support wakeup
sources on shared irq lines. And to be honest, it's utter bullshit.
The whole purpose of MSI is to avoid interrupt sharing, but of course
if that particular interrupt source has two potential causes, i.e. the
AER and the PME one and the stupid hardware does not support different
vectors or the drivers are not able to do so, it's conveniant to make
them shared instead of thinking about them what they really are:
Separate interrupts on a secondary interrupt controller connected to
the primary (MSI) one.
That's what is in fact. Simply because you can enable/disable them at
the same IP block quite contrary to stuff which is physically shared
by hard wired electrical connections.
Slapping IRQF_SHARED on that and then whining about shortcomings of
the core code is way simpler than sitting down and think about
actual topologies, right?
Most architectures aside of x86 have long ago realized that and the
core has all infrastructure available to deal with irq topologies. You
just have to utilize it.
Thanks,
tglx
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