Nguyen, Tom L writes: > The standard PCI Specification calls out SERR and PERR. I am not sure > about the recent discussion of PCI error of recovery. It is perhaps > regarding the possibility of recovering from a PERR or SERR. However, > PCI Express error occurs on the PCI Express link or on behalf of > transactions occurred on the PCI Express link. PCI Express component, > which implements PCI Express Advanced Error Reporting Capability, sends > error message to the Root Port to indicate error occurred on the PCI > Express link where it is connected. The PCI Express error recovery is on > behalf of attempting to do a PCI Express link recovery, not PCI error > recovery. It appears that PCI Express AER is disjoint from PCI error > recovery.
To give you some context, the recent discussion was about how we could give a unified interface to drivers for both PCI-Express error reporting and for the "Enhanced Error Handling" (EEH) facilities we have on IBM PPC64 boxes. EEH includes not only the detection and reporting of errors (for PCI, PCI-X and PCI-Express buses) but also hardware support for isolating devices when an error is detected, plus means for resetting individual bus segments or slots, to assist in recovering a device which has got into a bad state. Does PCI Express provide any facilities for recovering from errors, beyond just "try that transaction again"? Paul. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
