On Thu, Jul 10, 2014 at 11:03:43AM -0700, Havard Skinnemoen wrote:
> For non-shared banks, we might risk some CPUs not being able to
> poll their banks in a long time if they happen to be more or less
> synchronized with a different CPU. This will also get worse with
> shorter polling intervals, and with larger numbers of CPUs.
No, I meant to do something like
if (atomic_dec_and_test(&mce_banks[i].poll))
m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
atomic_add_unless(&mce_banks[i].poll, 1, 1);
so that you have only one CPU read the status register of mce_banks[i].
For non-shared banks, this will always work because no other CPU will
dec that variable anyway.
Or am I missing something...?
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
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