On Wed, Jun 11, 2014 at 10:54:48AM +0200, Peter Zijlstra wrote: > > I'm not sure about exact behavior of CondChgd bit, in particular when > > this bit is set. Although I read Intel System Programmer's Manual to > > figure out but I have yet completed that. At least, I think ignoring > > CondChgd bit should be enough for NMI watchdog perspective. > > So yes, the SDM lists the bit as existing but never once mentions it > outside of that, and its been doing that at least back to 2008. > > Ooh, I found it: > > "The IA32_PERF_GLOBAL_STATUS MSR also provides a ‘sticky bit’ to > indicate changes to the state of performance monitoring hardware (see > Figure 18-29)." > > Which is of course completely useless, not to mention inconsistent with > the later CondChgd name. > > HPA, can you explain wtf that bit does and why hatayama-san's ivb feels > like having that set on boot?
Matt found in the MSR listing for GLOBAL_STATUS: 63 CondChg: status bits of this register has changed. If CPUID.0AH: EAX[7:0] > 0 Which brings us to a grand total of 3 different names for this bit. If it indeed does what it says on the tin, set every time the status changes its like the most useless bit ever and I wonder why people bothered to spend silicon on it. In any case, the proposed patch seems fine, just needs a better changelog.
pgp0LX_msu2vf.pgp
Description: PGP signature
