From: Tuomas Tynkkynen <ttynkky...@nvidia.com>
3.12-stable review patch. If anyone has any objections, please let me know.
===============
commit d2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 upstream.
The value written to PLLE_AUX was incorrect due to a wrong variable
being used. Without this fix SATA does not work.
Signed-off-by: Tuomas Tynkkynen <ttynkky...@nvidia.com>
Tested-by: Mikko Perttunen <mperttu...@nvidia.com>
Reviewed-by: Thierry Reding <tred...@nvidia.com>
Tested-by: Thierry Reding <tred...@nvidia.com>
Acked-by: Thierry Reding <tred...@nvidia.com>
Signed-off-by: Mike Turquette <mturque...@linaro.org>
[mturque...@linaro.org: improved changelog]
Signed-off-by: Jiri Slaby <jsl...@suse.cz>
---
drivers/clk/tegra/clk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index e09f09ce44f8..4c1d9bbe3191 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1594,7 +1594,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char
*name,
"pll_re_vco");
} else {
val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
- pll_writel(val, pll_params->aux_reg, pll);
+ pll_writel(val_aux, pll_params->aux_reg, pll);
}
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
--
1.9.3
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