On Tue, 2014-05-27 at 20:32 +0100, Will Deacon wrote:
> Why would you need two barriers? I would have though an mmiowb() inlined
> into writel after the store operation would be sufficient. Or is this to
> ensure a non-relaxed write is ordered with respect to a relaxed write?
Well, so the non-relaxed writel would have to do:
sync
store
sync
The first sync is to synchronize with DMAs, so that a sequence of
store to mem
writel
Remains ordered vs. the device (ie, when the writel causes the device
to do a DMA, it will see the previous store to mem).
The second sync is needed as mmiowb, to order with unlocks.
At this point, I'm keen on keeping my per-cpu trick to avoid that
second one in most cases.
> Anyway, we may need something similar for other architectures with mmiowb
> implementations:
>
> blackfin
> frv
> ia64
> mips
> sh
>
> so I'm anticipating some more discussion when I try to push that patch :)
>
> Cheers,
>
> Will
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