On Wed, May 21, 2014 at 08:21:08AM -0700, Andy Lutomirski wrote: > On May 21, 2014 2:46 AM, "Borislav Petkov" <b...@alien8.de> wrote: > > > > On Tue, May 20, 2014 at 07:39:31PM -0700, Andy Lutomirski wrote: > > > So the issue here is that we can have an NMI followed immediately by > > > an MCE. > > > > That part might need clarification for me: #MC is higher prio interrupt > > than NMI so a machine check exception can interrupt the NMI handler at > > any point. > > Except that NMI can interrupt #MC at any point as well, I think.
No, #MC is higher prio than NMI, actually even the highest along with RESET#. And come to think of it, all exceptions which have a higher prio than NMI should touch that nmi_mce_nest_count thing. See Table 8-8 here: http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/24593_APM_v21.pdf That's the prios before 3, i.e. the NMI one. HOWEVER, this all is spoken with the assumption that higher prio interrupts can interrupt the NMI handler too at the first instruction boundary they've been recognized. The text is talking about simultaneous interrupts and not about interrupt handler preemption. But it must be because Steve wouldn't be dealing with exceptions in the NMI handler and nested NMIs otherwise... Hmmm. -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
